DESIGN OF FAULT-TOLERANT CHIP INTERFACES
Abstract and keywords
Abstract (English):
The article discusses the process of designing the interface of fault-tolerant chips. A redundant internal interface is designed for integrating system components on chips into a single information exchange system. The paper describes the interface for the four-channel construction of the VLSI chip of the BMC SNK. Special attention is paid to the description of interface signals.

Keywords:
design, fault tolerance, chips, VLSI interface, signal
References

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