Modeling of systems and processes Modeling of systems and processes Моделирование систем и процессов 2219-0767 89174 10.12737/2219-0767-2024-59-68 Технические науки Технические науки Formalization of topology and electrical circuit verification for computer-aided design systems Формализация верификации топологии и электрической схемы для систем автоматизированного проектирования Скворцова Татьяна Владимировна Skvortsova Tatyana Vladimirovna Зольников Константин Владимирович Zolnikov Konstantin Vladimirovich Плотников Алексей Михайлович Plotnikov Aleksey Mihaylovich Скоркин И. В. Scorkin I V Воронежский государственный лесотехнический университет имени Г.Ф. Морозова Voronezh State University of Forestry and Technologies named after G.F. Morozov Воронежский государственный лесотехнический университет имени Г.Ф. Морозова Россия Voronezh State University of Forestry and Technologies named after G.F. Morozov Russian Federation АО "Росэлектроника" Россия АО "Росэлектроника" Russian Federation АО "Научно-исследовательский институт космического приборостроения" Россия JSC «Research Institute of Space Instrumentation» Russian Federation 23 10 2024 23 10 2024 17 3 61 70 01 10 2024 30 09 2024 https://zh-szf.ru/en/nauka/article/89174/view

в статье рассматривается исследование методов проверки соответствия топологии и электрической схемы в электронных устройствах. Авторы представляют новый подход к анализу и верификации топологической структуры с учетом электрических характеристик, что приводит к повышению формализации задач и обеспечивает лучшую оптимизацию взаимодействия человека и компьютерной системы САПР. Исследование включает в себя анализ современных методов и инструментов, используемых в процессе разработки электронных устройств, а также предлагает инновационные подходы к обеспечению согласованности между топологией и электрической функциональностью. Выполняется LVS-проверка проекта с помощью Calibre, xRC-экстракция проекта, физическая верификация проекта средствами САПР Cadence Physical Verification System (PVS), LVS-проверки проекта с помощью PVS. Представляет подробный анализ процесса верификации интегральных схем, выполняемой с использованием современных инструментов САПР. В работе рассматриваются ключевые этапы верификации, включая LVS-проверку проекта с использованием инструмента Calibre, xRC-экстракцию проекта, а также физическую верификацию проекта средствами Cadence Physical Verification System (PVS). Особое внимание уделяется LVS-проверкам, представляющим собой важный этап проектирования, гарантирующий соответствие топологии и электрической схемы. Рассмотрены особенности использования Calibre для выполнения LVS-проверок, а также процесс xRC-экстракции для извлечения параметров резисторов и конденсаторов. Для физической верификации проекта использованы возможности Cadence PVS, обеспечивающего анализ соответствия физической реализации схемы заданным правилам. Полученные результаты и опыт, представленные в статье, могут быть полезными для инженеров и исследователей, занимающихся проектированием интегральных схем, а также для тех, кто интересуется применением современных инструментов САПР в области верификации и валидации электронных устройств

The article examines the study of methods for verifying the correspondence of topology and electrical circuit in electronic devices. The authors present a new approach to the analysis and verification of the topological structure, taking into ac-count electrical characteristics, which leads to an increase in the formalization of tasks and provides better optimization of human interaction and a computer CAD system. The research includes an analysis of modern methods and tools used in the development of electronic devices, and also offers innovative approaches to ensuring consistency between to-pology and electrical functionality. LVS verification of the project is performed using Calibre, xRC extraction of the project, physical verification of the project using CADENCE Physical Verification System (PVS), LVS verification of the project using PVS. Presents a detailed analysis of the inte-grated circuit verification process performed using modern CAD tools. The paper discusses the key stages of verifica-tion, including LVS verification of the project using the Cal-ibre tool, xRC extraction of the project, as well as physical verification of the project using Cadence Physical Verifica-tion System (PVS). Special attention is paid to LVS checks, which represent an important design stage that guarantees the compliance of the topology and the electrical circuit. The features of using Calibre to perform LVS checks, as well as the xRC extraction process to extract the parameters of re-sistors and capacitors, are considered. For the physical veri-fication of the project, the capabilities of Cadence PVS were used, which provides an analysis of the compliance of the physical implementation of the scheme with the specified rules. The results obtained and the experience presented in the article can be useful for engineers and researchers in-volved in the design of integrated circuits, as well as for those interested in the use of modern CAD tools in the field of verification and validation of electronic devices

 LVS-проверка проекта xRC-экстракция проекта физическая верификация проекта Cadence Physical Verification System LVS-проверки проекта Calibre LVS-project Verification xRC-project extraction Physical Project Verification Cadence Physical Verification System LVS-project verification Calibre

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