Russian Federation
Russian Federation
AO "Nauchno-issledovatel'skiy institut elektronnoy tehniki"
Russian Federation
UDK 501 Общие вопросы физикоматематических и химических наук
UDK 60 Прикладные науки. Общие вопросы
The theoretical propositions of the algebra of logic are considered. It is noted that the current microcircuitry based on the algebra of logic contains logical statements: true (yes) is a logical unit, false (no) is a logical zero. Based on the given logical function: ((ABC)×D + A×(BCD) + A×(BC)×D + (AB)×(CD), frontal, minimal, transformed minimal variants of the combination device are implemented, as well as minimized variants in the bases "AND-NOT" and "OR-NOT". A combination device based on import-substituting chips of 155, 176 series has been designed. The analysis of the obtained devices is made from the standpoint of technical and economic indicators, in particular, an assessment of the number of logic elements used, an assessment of the symmetry of the structure, as a result, a reduction in energy consumption, an increase in performance, improvements in parameters for reliability of functioning, a decrease in weight and size characteristics. Assuming that the law of change of the information parameter U1 is close to linear, taking into account the effect of temperature as boundary values for the elements of the applied microcircuits, taking the values -60 °C and +120°. Accordingly, the parametric reliability of the optimal implementation of the device according to the output voltage parameter is calculated. The conclusion is made about the inverse dependence of parametric reliability on temperature growth. A recommendation is given when evaluating parametric reliability for a number of other information parameters about the need to take into account both the number of chips used and the type of their interconnections.
Combination device, AND-NOT, OR-NOT, K155LA1, K155LA3, K176LA7, K176LA8, parametric reliability
1. Solomatin, N.M. Logicheskie elementy EVM / N.M. Solomatin. - M. : Vysshaya shkola, 1990. - 160 s.
2. Proektirovanie interfeysov sboeustoychivyh mikroshem / V.K. Zol'nikov, N.V. Mozgovoy, S.V. Grechanyy [i dr.] // Modelirovanie sistem i processov. - 2020. - T. 13, № 1. - S. 17-24. - DOI:https://doi.org/10.12737/2219-0767-2020-13-1-17-24.
3. Reconfigurable Boolean Logic in Memristive Crossbar: The Principle and Implementation / S.Y. Hu, Y. Li, L. Cheng [et al.] // IEEE Electron Device Letters. - 2018. - Vol. PP(99). - Pp. 1-1. - DOI:https://doi.org/10.1109/LED.2018.2886364.
4. Metody kontrolya nadezhnosti pri razrabotke mikroshem / K.V. Zol'nikov, S.A. Evdokimova, T.V. Skvorcova, A.E. Gridnev // Modelirovanie sistem i processov. - 2020. - T. 13, № 1. - S. 39-45. - DOI:https://doi.org/10.12737/2219-0767-2020-13-1-39-45.
5. Efficient Implementation of Boolean and Full-Adder Functions With 1T1R RRAMs for Beyond Von Neumann In-Memory Computing / Z.R. Wang, Y. Li, Y.T. Su [et al.] // IEEE Transactions on Electron Devices. - 2018. - Vol. PP (99). - Pp.1-8. - DOI:https://doi.org/10.1109/TED.2018.2866048.
6. Boolean and Sequential Logic in a One-Memristor-One-Resistor (1M1R) Structure for In-Memory Computing / Y. Zhou, Y. Li, N. Duan [et al.] // Advanced Electronic Materials. - 2018. - Vol. 4. - DOI:https://doi.org/10.1002/aelm.201800229.
7. Zmeev, A.A. Ocenki vzaimosvyazi mezhdu znachimost'yu komand dlya realizacii NSD k gipervizoru cherez virtual'nuyu mashinu na osnove metodov nechetkoy logiki / A.A. Zmeev // Modelirovanie sistem i processov. - 2020. - T. 13, № 2. - S. 33-39. - DOI:https://doi.org/10.12737/2219-0767-2020-13-2-33-39.
8. Easily Cascaded Memristor-CMOS Hybrid Circuit for High-Efficiency Boolean Logic Implementation / Z. Dong, D. Qi, Y. He [et al.] // International Journal of Bifurcation and Chaos. - 2018. - Vol. 28(12). - P. 1850149. - DOI:https://doi.org/10.1142/S0218127418501493.
9. Carlet, C. Boolean functions for cryptography and error correcting codes / C. Carlet, Y. Crama, P. Hammer // Boolean Models and Methods, Computer Science. - 2010. - Vol. 2. - P. 257. - DOI:https://doi.org/10.1017/CBO9780511780448.011.
10. Yur'ev, N.Yu. Analiz eksperimenta po sozdaniyu tokoprovodyaschih dorozhek pechatnyh plat / N.Yu. Yur'ev, V.V. Lavlinskiy, N.S. Bokareva // Modelirovanie sistem i processov. - 2020. - T. 13, № 2. - S. 77-84. - DOI:https://doi.org/10.12737/2219-0767-2020-13-2-77-84.
11. Osobennosti proektirovaniya bazovyh elementov mikroshem kosmicheskogo naznacheniya / V.K. Zol'nikov, T.V. Skvorcova, I.I. Strukov [i dr.] // Modelirovanie sistem i processov. - 2020. - T. 13, № 3. - S. 66-70. - DOI:https://doi.org/10.12737/2219-0767-2020-13-3-66-70.
12. Carlet, C. A larger class of cryptographic Boolean functions via a study of the Maiorana-McFarland construction / C. Carlet // Annual International Cryptology Conference. - 2002. - P. 549. - DOI:https://doi.org/10.1007/3-540-45708-9_35.
13. Cryptographic Boolean Functions: One Output, Many Design Criteria / S. Picek, D. Jakobovic, J. Miller [et al.] // Applied Soft Computing. - 2015. - Vol. 40. - DOI:https://doi.org/10.1016/j.asoc.2015.10.066.
14. Zol'nikov, V.K. Modelirovanie rabotosposobnosti mikroshem na razlichnyh ierarhicheskih urovnyah opisaniya v SAPR / V.K. Zol'nikov, A.L. Savchenko, A.Yu. Kulay // Modelirovanie sistem i processov. - 2019. - T. 12, № 1. - S. 30-39. - DOI:https://doi.org/10.12737/article_5d639c80dafac1.08243981.
15. Grechanyy, S.V. Metody obespecheniya stoykosti k TZCh dlya upravlyayuschey logiki i staticheskoy pamyati mikroprocessora pri proektirovanii / S.V. Grechanyy, K.A. Chubur // Modelirovanie sistem i processov. - 2019. - T. 12, № 4. - S. 17-24. - DOI:https://doi.org/10.12737/2219-0767-2020-12-4-17-24.
16. Analiz kachestva proektirovaniya blokov OZU v sostave mikroprocessornyh sistem s obespecheniem minimal'noy sboeustoychivosti / V.K. Zol'nikov, Yu.A. Chevychelov, V.V. Lavlinskiy [i dr.] // Modelirovanie sistem i processov. - 2019. - T. 12, № 4. - S. 47-55. - DOI:https://doi.org/10.12737/2219-0767-2020-12-4-47-55.
17. Analiz proektirovaniya blokov RISC-processora s uchetom sboeustoychivosti / V.K. Zol'nikov, A.S. Yagodkin, V.I. Anciferova [i dr.] // Modelirovanie sistem i processov. - 2019. - T. 12, № 4. - S. 56-65. - DOI:https://doi.org/10.12737/2219-0767-2020-12-4-56-65.
18. Postroenie intellektual'nyh sistem upravleniya informacionnymi processami v usloviyah neopredelennosti / Yu.Yu. Gromov, V.E. Didrih, I.V. Didrih, A.Yu. Grechushkina // Modelirovanie sistem i processov. - 2018. - T. 11, № 1. - S. 10-14. - DOI:https://doi.org/10.12737/article_5b574c7c299958.66418026.
19. Sozdanie bazisa dlya mikroshem sbora i obrabotki dannyh / V.A. Sklyar, A.V. Achkasov, K.V. Zol'nikov [i dr.] // Modelirovanie sistem i processov. - 2018. - T. 11, № 2. - S.66-71. - DOI:https://doi.org/10.12737/article_5b57795062f199.54387613.
20. Zhang, W. Improving the lower bound on the maximum nonlinearity of 1-resilient Boolean functions and designing functions satisfying all cryptographic criteria / W. Zhang, E. Pasalic // Information Sciences. - 2016. - Vol. 376. - DOI:https://doi.org/10.1016/j.ins.2016.10.001.
21. Shemotehnicheskiy bazis i proverka mikroshem na rabotosposobnost' / V.K. Zol'nikov, S.A. Evdokimova, A.V. Fomichev [i dr.] // Modelirovanie sistem i processov. - 2018. - T. 11, № 4. - S. 25-30. - DOI:https://doi.org/10.12737/article_5c79642c158bc0.44957273.
22. Tang, D. Highly nonlinear boolean functions with optimal algebraic immunity and good behavior against fast algebraic attacks / D. Tang, C. Carlet, X. Tang // IACR Cryptology ePrint Archive. - 2011. - № 1. - P. 366.
23. Usloviya ekspluatacii novogo pokoleniya mikroshem special'nogo naznacheniya / V.K. Zol'nikov, V.P. Kryukov, A.Yu. Kulay [i dr.] // Modelirovanie sistem i processov. - 2017. - T. 10, № 1. - S. 23-26. - DOI:https://doi.org/10.12737/article_5926f7b17e1be3.07188434.
24. Sozdanie shemotehnicheskogo i konstruktivno-tehnologicheskogo bazisa mikroshem special'nogo naznacheniya / V.K. Zol'nikov, V.P. Kryukov, A.Yu. Kulay [i dr.] // Modelirovanie sistem i processov. - 2017. - T. 10, № 1. - S. 27-29. - DOI:https://doi.org/10.12737/article_5926f7b182b2f7.65479593.
25. Yudina, N.Yu. Analiz faktorov, okazyvayuschih vliyanie na nadezhnost' strukturnyh elementov slozhnyh vychislitel'nyh sistem / N.Yu. Yudina, A.N. Kovalev // Modelirovanie sistem i processov. - 2017. - T. 10, № 3. - S. 86-93. - DOI:https://doi.org/10.12737/article_5a2928416cdb36.94937249.
26. Shagurin, I.I. Tranzistorno-tranzistornye logicheskie shemy / I.I. Shagurin. - M., 1974. - 158 s.
27. Presnuhin, L.N. Raschet elementov cifrovyh ustroystv / L.N. Presnuhin, N.V. Vorob'ev, A.A. Shishkevich. - M. : Vysshaya shkola, 1991. - 526 s.
